Digital Physical Implementation
EDA Solutions offers a productive and cost-effective solution to most customer's needs in mixed signal ASIC design. Targeting "Big-A Little-D" designs in the mainstream mixed signal technologies down to 28nm, the heart of the solutions is the Mentor, Tanner AMS IC design flow.
Bringing together a sophisticated flow with Mentor's Oasys-RTL which provides a physical RTL synthesis solution with fast runtimes, improved QoR, and physical awareness by optimizing the design at a higher level of abstraction and using integrated floorplanning and placement capabilities. This synthesis solution uses a patented PlaceFirst technology to pull placement ahead of synthesis, so physical placement information is available for accurate timing and congestion analysis.
Place and Route
Tanner Nitro-SoC Place & Route (P&R) is fully integrated with L-Edit to address the physical implementation of the digital needs of Analog-on-Top (AoT) designs. For those digitally-assisted analog designs there is increasing amounts of digital content to enhance analog capabilities such as automated calibration and more programmability. Tanner P&R is the ideal cost effective solution. Its streamlined user interface helps quickly place and route the control block of an ADC by importing technology data user such as LEF, Liberty and PTF files, specify the Verilog netlist to use and define timing requirements by specifying your clocks or via a SDC file.
Define flootplan and power plan requirements
And for floorplan requirements, you can specify chip size, margins, & row site names, or define the requirements in the layout or via a DEF floorplan file. When setting power requirements, you can specify power/gnd ring and stripe parameters, or define the requirements in the layout or via a DEF floorplan file. Once setup, you can perform the place and route view the results in L-Edit.
For more details follow these links to the respective pages on partner websites.
Digital Physical Implementation Software Tools
- Oasys-RTL Physical RTL synthesis
- Tanner EDA Place and Route
- Silicon test and yield analysis - Tessent