S-Edit increases your design productivity while handling the most complex IC designs. This powerful environment supports fast, 64-bit rendering and cross-probing between schematic, layout, simulator and LVS reporting at net and device levels.
Instances in the schematic are linked to simulation models for the designers choice of behavioural modelling from transistor level SPICE to HDL blocks (Verilog or VHDL). Out of the box, S-Edit is integrated with several analog transistor level simulators and mixed signal simulation platforms to suit the users needs. The primary solutions are AFS for SPICE simulation and Symphony for co-simulation with digital portions of a design.
- Native on OpenAccess
- Multiple-views per cell to support Analog Mixed-Signal Design including: SPICE, schematic, Verilog, Verilog-A, layout, Verilog-AMS, VHDL, and VHDL-AMS views
- Supported by over 180 PDK’s from more than 30 foundries
- Fully scriptable and expandable using TCL/Tk command language
- Advanced array and bus support
- Compare two schematics and visually displays the differences
- Available for Linux and Windows