S-Edit increases your design productivity while handling the most complex IC designs. This powerful environment supports fast, 64-bit rendering and cross-probing between schematic, layout, simulator and LVS reporting at net and device levels.
Instances in the schematic are linked to simulation models for the designers choice of behavioural modelling from transistor level SPICE to HDL blocks (Verilog or VHDL). Out of the box, S-Edit is integrated with several analog transistor level simulators and mixed signal simulation platforms to suit the users needs. These include AFS, Eldo and T-Spice simulators for SPICE simulation and Questa ADMS and Symphony for co-simulation with digital portions of a design.
- Industry-standard support including comprehensive SPICE simulator integration
- Directly view operating point simulation results in the schematic
- Cross-probe between schematic, layout and LVS report with net/device highlighting
- Configurable schematic Electrical Rule Checks (ERC)
- Advanced array and bus support
- Integrated with Tanner L-Edit to speed the layout and ECO process
- Available for Linux and Windows