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Memory IP (Novelics)

The Novellics embedded Memory IP seeks to achieve optimum dynamic power, leakage, density, speed, reliability and cost for low-power and high-performance ASIC, ASSP, and SoC designs. These memory IPs are implemented with the standard logic CMOS process with no additional masks or process steps to minimize cost and to maximize reliability and portability. Users of this Memory compete in low-power consumer, wireless, high-speed computing, industrial, and networking applications.


SOURCE URL: https://www.mentor.com/products/ip/memory-ip/