Calibre xRC Extraction
Performance and accuracy for all designs and nodes Calibre xRC parasitic extraction enables seamless creation of netlists and parasitic debugging in the design environment. The flexible data model supports diverse design flows and styles, including analog, memory, ASIC, and mixed signal. Foundry-qualified for virtually all processes and nodes. Offers analog…
Aprisa SoC Design
The Aprisa place-and-route platform is a detail-route-centric solution to the challenges of modern digital IC implementation.
Calibre® One DRC/LVS/xRC
The Calibre One IC verification suite is an integral part of the Custom IC analog/mixed-signal (AMS) physical design environment, creating an easy path to the proven capabilities of Calibre verification tools.
