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Performance and accuracy for all designs and nodes

Calibre xRC parasitic extraction enables seamless creation of netlists and parasitic debugging in the design environment. The flexible data model supports diverse design flows and styles, including analog, memory, ASIC, and mixed signal. Foundry-qualified for virtually all processes and nodes.

Offers analog mixed-signal SoC designers a single parasitic extraction solution that is independent of design style or flow.


High-performance rule-based parasitic extraction

Advanced extraction and process models correlate closely with field solver results; proprietary reduction algorithm maintains integrity of parasitic data. Reduces need for prohibitive design margins by incorporating manufacturing-dependent effects (e.g., in-die variation) into parasitic models.


Integrated Calibre verification flow

The Calibre xRC tools exchange native database information with Calibre nmLVS, Calibre PERC, and Calibre xACT 3D products. Upstream design integration using Calibre interfaces enables GUI-driven launch, back annotation, and cross-probing for all popular layout environments. Fully compatible with downstream digital, custom, and mixed-signal flows.


Full-chip performance

Combines the performance of the Calibre hierarchical and multi-threaded architecture with a compact netlist to boost throughput of large designs and maintain rapid feedback within custom design environments. Multiple process corner analysis does not require complete design re-run.