Time-to-market pressures and design complexity push ASIC and SoC verification teams to rethink traditional approaches which are insufficient for full-system validation. Engineers face long runtimes, limited visibility and late-stage bug discovery—issues that can delay projects and increase risk.
Siemens EDA’s Hardware Assisted Verification (HAV) solutions address these challenges by providing scalable platforms for high-speed prototyping and emulation. In our recent October team
meeting, Romain Petit, Product Manager for Software Prototyping (FPGA Based Prototyping), presented an overview of Siemens’ HAV technologies, with a focus on the Veloce proFPGA CS platform.
Why Hardware-Assisted Verification?
Simulation alone often can’t keep up with the verification demands of modern SoCs. Hardware-assisted approaches—using FPGAs or emulators—enable engineers to run designs at near real-time speeds, validate system-level interactions and begin software development earlier in the cycle.
This is particularly useful for:
- Pre-silicon software development
- System-level validation
- Regression testing
- Debugging complex interactions across IP blocks
Overview of proFPGA
The Veloce proFPGA CS platform is Siemens EDA’s latest generation modular FPGA-based prototyping system. It supports a range of use cases, from IP-level validation to full-chip prototyping. Key technical features include:
- Scalability: Supports configurations from single FPGA boards to multi-board systems for large SoCs.
- High-speed interfaces: Enables integration with real-world I/O and peripherals.
- Debug capabilities: Offers signal visibility, trace capture, and integration with software debuggers.
- Toolchain integration: Works with Siemens’ simulation and emulation tools for unified flow.
Engineers can use proFPGA to validate hardware and software concurrently, reducing the time between design completion and tape-out.
Use cases and benefits
Customers using Siemens HAV solutions report improvements in:
- Verification throughput: Faster execution of test suites and regression runs.
- Bug detection: Earlier identification of system-level issues that are hard to catch in simulation.
- Software readiness: Ability to start firmware and driver development before silicon availability.
- Design iteration: Faster turnaround for design changes and validation.
Industries with high reliability requirements—such as automotive, aerospace, and industrial—benefit from the ability to validate safety-critical systems under realistic conditions.
Integration and workflow
Veloce proFPGA integrates with Siemens EDA’s broader EDA ecosystem, including simulation (Questa), emulation (Veloce Strato CS) and formal verification tools. This allows teams to move between abstraction levels without disrupting the verification flow.
For example:
- Use simulation for early RTL validation.
- Move to proFPGA for system-level testing and software bring-up.
- Use emulation for full-chip performance analysis and power estimation
Conclusion
Hardware-assisted verification is becoming a standard part of the ASIC and SoC development process. Siemens EDA’s Veloce proFPGA CS platform offers a practical, scalable solution for teams looking to improve verification efficiency and reduce time-to-market.
At EDA Solutions, we support engineering teams in deploying these technologies effectively. If you’re exploring HAV for your next project, we’re here to help with technical guidance and integration support.