Why Schematic-Correct Designs Fail at Advanced Nodes – Post-Layout Reality in Specialty I/O Verification [webinar]

Sofics and EDA Solutions are back with another live webinar to explore why schematic‑correct designs can fail at advanced nodes and how post‑layout verification is essential for reliable specialty I/O and custom IC design. Drawing on real production experience, Sofics will share insights into the design and verification of analogue and specialty I/O circuits in advanced CMOS and FinFET technologies. The session highlights how layout‑sensitive effects can significantly impact final silicon behaviour and why advanced post‑layout extracted simulation is now critical to achieving robust, first‑time‑right designs. The webinar is divided into two parts.

In the first part, Khalid Teama, Technical Director at EDA Solutions, introduces the Siemens EDA Custom IC technologies that underpin Sofics’ production verification flow. He will explain how Solido™ Simulation Suite, together with Calibre® Parasitic Extraction (xRC, xACT and xACT 3D), enables large‑scale transient, corner and Monte Carlo analyses to be performed with realistic turnaround times, while maintaining strong correlation to golden SPICE results. This combination allows designers to efficiently evaluate circuit behaviour across operating conditions and statistical variations, with high confidence in accuracy.

In the second part, Rani Baetens, Analog Design Engineer at Sofics, presents two recent production design cases that demonstrate why schematic‑level correctness is no longer sufficient in advanced nodes. One case examines a low‑power bias generator for specialty I/O in a 4 nm process, where post‑layout extraction revealed layout‑induced leakage paths. The second focuses on a dual‑voltage I/O design in TSMC 22 nm CMOS, where extracted simulations exposed well‑proximity effects that were not visible before layout.

Together, these examples illustrate how extracted simulation provides deeper insight, reduces risk and increases confidence prior to tape‑out.