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The Questa Advanced Simulator is the core simulation and debug engine of the Questa Verification Solution; the comprehensive advanced verification platform capable of reducing the risk of validating complex FPGA and SoC designs.

Questa achieves industry-leading performance and capacity through very aggressive, global compile and simulation optimisation algorithms for SystemVerilog and VHDL.

INDUSTRY-LEADINGulti-core simulation

Questa Advanced Simulation achieves industry-leading performance and capacity through very aggressive, global compile and simulation optimization algorithms of SystemVerilog and VHDL, improving SystemVerilog and mixed VHDL/SystemVerilog RTL simulation performance by up to 10X.

MULTI-CORE SIMULATION

The Questa Advanced simulator supports all design languages and constructs, and either automatically or manually partitions the design to run in parallel while maintaining a single database for debug and coverage.

AUTOMATED STIMULII GENERATION

The Questa Advanced Simulator supports the most comprehensive solutions for test-bench automation in the industry, enabling automatic creation of complex, input-stimuli using SystemVerilog or SystemC Verification (SCV) library constructs, and combining these forms of stimulus generation with functional coverage to identify the functionality exercised by the automatically-generated stimulus.