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Control Parsing of SPICE, Verilog and VHDL Views in S-Edit

Published by Khalid Teama – Latest update: 25/03/2022

ID: TN031
Relevant product(s): S-Edit
Operating systems: RHEL / Windows
Versions affected: 2021.2 and above
Relevant area(s): Usage


Large netlist views in S-Edit (Verilog, VHDL, SPICE) can affect the tool performance. A workaround was introduced to allow the users to control how much S-Edit can parse such views. In certain cases, not parsing the netlist view can prevent S-Edit from netlisting the subcircuits that make up the netlist, for example in case of a digital block in CDL format, S-Edit may not netlist the subcircuits (standard cells) which might cause issues downstream in LVS.


Parsing of Spice, Verilog or VHDL views now has three modes that can be used to control performance.

  • full — parse the entire netlist
  • interface — only parse interfaces
  • none — do not parse the netlist

The mode is automatically chosen, but can be overridden by placing a property on the view called “PARSE” with one of the above values. Verilog and VHDL views have “full” and “none” modes, but do not support “interface”.

To use this feature:

  • Please open the netlist view of the concerned block so you see the text editor context in S-Edit
  • In the “Property Window”, add a property named “PARSE” and set the value to “full” or any of the above values, the type of the property is “String”
  • Save and attempt netlisting