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Variation-aware design and verification for memory, analog/RF, and standard cell

Solido™ Variation Designer™ software is the industry’s most advanced variation-aware design solution, used by top semiconductor companies and foundries.

Utilising machine learning, it delivers unprecedented speed, accuracy, and variation coverage.

To meet specifications and to stay competitive in designing the best-performing quality chip, designers need to perform extensive SPICE simulations to account for all the potential design variation. Variation Designer enables full design coverage in orders-of-magnitude fewer simulations, but with the accuracy of brute force techniques.



Key Product Functionality

Solido Variation Designer is a comprehensive suite of tools for variation-aware design and verification. The tools operate on semiconductor ICs across memory, analog, RF, mixed-signal, and standard cell design.

Variation Designer for Memory

Full-chip memory and cell-level verification

  • High-sigma verification of columns, bitcells, sense amps, and other memory blocks
  • Full-chip memory verification with perfect statistical accuracy
  • 1,000,000X faster than brute force Monte Carlo simulation for 6-sigma
  • Powerful command line interface for batch mode operation

Variation Designer for Analog/RF

Fast, accurate verification and debug

  • 2-50X faster verification across PVT corners
  • 10X faster 3-sigma Monte Carlo for 1 PVT
  • 100X faster 3-sigma Monte Carlo for many PVTs
  •  Rapid interactive design and debug with Monte Carlo and SPICE accuracy

Variation Designer for Standard Cell

Comprehensive verification of full cell libraries

  • 10-1000X faster high-sigma verification and debug of full cell libraries
  • Fast, accurate verification of statistical timing models and critical paths
  • Fast cell library optimization across PVT and statistical corners
  • Powerful command line interface for batch mode operation