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02 Jun 2009
LFoundry Releases Low Power and RF 0.15 μm PDK
New PDK supports analog design flow from schematic entry and simulation, through schematic-driven layout with parameterisable cells, to full custom layout and verification.

Landshut & Munich, Germany (June 2nd, 2009) - LFoundry today announced the availability of a high performance process design kit (PDK) for A/MS electronic designs, developed using Tanner EDA's HiPer Silicon™ software, for its LF150 modular 0.15 μm Low Power and RF CMOS process. This grants Tanner EDA customers access to Europe's leading pure-play foundry CMOS technology.

LFoundry is providing Tanner EDA users with the LF150 modular 0.15 μm Low Power and RF CMOS process that provides up to six levels of aluminium interconnect, a polymide passivation and I/O voltages of 1.8V, 3.3V and 5.0V. Optionally a MiM capacitor is also available. The process is based on a 0.15 μm CMOS proven technology and offers excellent versatility for ASIC designers.

In addition to schematic and layout libraries for full custom analog design, LFoundry provides a cell library with standard cells and periphery cells.

LFoundry offers a cost-efficient rapid prototyping service, known as Multi-Project Wafer (MPW) with the most frequent schedule currently offered in the industry. LFoundry will provide special incentives to their initial customers requesting participation in the service through to July 2009.

Gerhard Spitzlsperger, CTO of LFoundry explains "Tanner Tools are an excellent choice for ASIC designers who want to tape out a high performance chip in LF150 technology with reasonable costs for design tooling".

"The release of LFoundry process design kit offers easy, reliable access to a low power and RF process for the 1000's of worldwide Tanner EDA customers," comments Paul Double, Managing Director of Tanner EDA's European distributor EDA Solutions. "Coupled with the comprehensive functionality, productivity and ease of use of the Tanner EDA IC Design tools, the use of this process design kit can minimise design time and risk, thus speeding concept to silicon."