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18 Apr 2007
MOSIS delivers economical access to IBM 65nm process
MOSIS, a provider of low-cost prototyping and small volume production services for custom ASICs, announces access to IBM�s 65nm silicon foundry process through its multi-project wafer (MPW) service. The service means that system-on-chip designers can obtain samples or small production quantities of digital or mixed-signal devices at less than 10% of the cost of using a dedicated production run. Sharing masks and wafers with other chip designs achieves this. MOSIS also offers die packaging and test.

65nm is the smallest process geometry presently available through MPW services. It is typically used for high-performance, high volume applications in wired and wireless communications, and in digital media. The process is also suited to very low power chip designs.

Users of the MOSIS service pay only for the silicon area occupied by their designs; costs are not shared equally based on the number of users. Deputy Director of the MOSIS service, Wes Hansford, comments, "Many chip designers still believe that it takes millions of dollars to create a sub-micron design using a leading-edge process. This is restricting innovation. The MOSIS service removes the barrier and makes access to leading-edge processes affordable."