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10 Mar 2008
Tanner EDA upgrades chip design tool suite
Tanner Tools V13.0 cuts development time in simulation, layout and verification for analog and mixed-signal ICs and MEMS devices

Tanner Tools V13.0 is a significant upgrade to Tanner EDA's Windows-based tool suite for analog and mixed-signal IC and MEMS design. Tanner Tools consists of S-Edit for schematic capture, T-Spice for simulation, L-Edit for layout and HiPer Verify for design verification. The latest upgrade adds Verilog-A model support to T-Spice. L-Edit is boosted with better library support, improvements in schematic driven layout (SDL) and a new SDL automatic router. HiPer Verify gets a hierarchical, foundry-compatible netlist extraction tool � HiPer Extract. In addition, Tanner have added HiPer PX, a 3D RC extraction tool, allowing accurate 3D extraction of interconnect parasitics.



Verilog-A support allows much faster simulations to be made using the latest Verilog-A models from foundries. Users can easily model complete circuit blocks or systems, accelerating design time and reducing cost.
Tiburon Design Automation�s Verilog-A module has been added to the T-Spice simulator to provide this functionality. Models are compatible with Cadence, HSpice, SmartSpice, ADS and others.



L-Edit's SDL has been improved with automatic update of flylines during placement, the ability to view pins by net or by instance, and routing geometry tagged with the user's intended net, allowing selection and rip-up of objects by net.
An optional SDL all-layer, gridless router is optimized for analog layout, block interconnect and chip assembly. It allows the designer to manually route critical nets in an analog design, then automatically, and rapidly, route the rest.



HiPer PX, which was first demonstrated last year, is now available within L-Edit. It provides 2D and 3D resistance and capacitance (RC) extraction for accurate modeling of parasitics both across metal layers and between the metal layers and the chip substrate.
The designer can choose between fast, hierarchical 2D or flat, highly accurate 3D extraction, or use a combination of both techniques in different parts of the circuit to obtain the optimum level of data.

A new addition to HiPer Verify, HiPer Extract provides foundry-compatible netlist extraction. It will read Calibre and Dracula command files and extract a hierarchical netlist for LVS. The tool extracts the same level of parasitics as Calibre, including those of devices and simple interconnects.

Commenting on the changes in Tanner Tools V13.0, Daniel Hamon, General Manager, Tanner EDA, said, "This is a major productivity upgrade affecting the design flow from simulation through to design verification. In conjunction with the latest version of our schematic capture tool, S-Edit, Tanner Tools V13.0 will enable designers to get their devices to market much faster than ever before, and at about one tenth of the cost of using tools from the largest EDA players. Tanner Tools V13.0 is an unrivalled value proposition for companies that want to be productive in the shortest possible time and don't want to waste money on tool functions they will rarely or never use."

All the benefits of Tanner Tools V13.0 are featured in the companyss HiPer Silicon package, which is available now, priced from 40,000 per seat.
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