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10 Mar 2010
Tanner EDA and IC Mask Design Collaborate to Accelerate Analog Layout Design
Tanner EDA, the catalyst for innovation for the design, layout and verification of analog and mixed-signal integrated circuits (ICs) and IC Mask Design, an industry leader in the provision of physical design services to the global semiconductor industry, are collaborating on the development of a toolset to accelerate analog layout design. By exclusively licensing IC Mask Design�s patented layout acceleration technology and integrating it into Tanner EDA�s custom IC design suite, the partners will offer
engineers an improved solution to boost layout productivity and quality.

Tanner EDA and IC Mask Design have been working together since 2007. In the course of working with customers to better understand their analog layout design challenges, the partners recognized a need to speed up the
analog layout process. In Q2 2010 Tanner EDA will offer a breakthrough toolset based on IC Mask Design�s proprietary technology that accelerates and semi-automates physical design activities to improve productivity. The new tool will embed seamlessly into Tanner EDA�s powerful and robust layout editor. Designers will be able to automatically generate devices and structures that are silicon-aware and are contextually tuned for their own specific layouts. This new solution gives engineers and managers the benefits of quality and productivity by consistently applying analog layout knowledge and experience to eliminate errors and speed layout cycles.

Commenting on the collaboration, Greg Lebsack, president of Tanner EDA, said, �We are very focused on bringing innovations from trusted, well-regarded partners to our customers, and are pleased to be able to help them
benefit from the depth and breadth of IC Mask Design�s experience in analog layout design. This collaboration is another instance of our desire to help analog designers develop breakthrough products with improved productivity and shorter design cycle times.�

Mr. Ciaran Whyte, co-founder and CTO of IC Mask Design, added, �We have always been impressed with the functionality and ease-of-use that Tanner EDA�s tools deliver to designers. It has been a natural extension of our working relationship to leverage our joint knowledge
of analog layout challenges to further benefit analog layout productivity.�

Previews of the joint solution developed by Tanner EDA and IC Mask Design will be available from March 9th to March 12th in Booth #12 at the Design Automation & Test in Europe (DATE) conference in Dresden, Germany. The partners expect to ship this tool along with Tanner EDA�s next major product release � v15 of HiPer
Silicon� � at the beginning of Q2, 2010.
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