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A Complete
Suite of Tools for the Professional T-Spice Pro™ offers fast and accurate simulation for analog and mixed analog/digital circuits. Full chip designs where more than 300,000 elements can be simulated. W-Edit streamlines and customizes graphical data representation using data files without modification from T-Spice and GateSim simulation runs. LVS accurately and efficiently compares two SPICE netlists. LVS can use topological information, parametric values, or geometric values to compare netlists with a specified tolerance. L-Edit™ is a full-featured, high-performance, interactive graphical mask layout editor. L-Edit generates layouts quickly and easily, supports fully hierarchical designs, and allows an unlimited number of layers, cells, and levels of hierarchy. L-Edit/DRC™ is a user-configurable design rule checker that can verify a full chip or just a specific region. Easy portability across platforms allows you to move large DRC runs to higher performance or multitasking hardware. L-Edit/Extract™ creates SPICE-compatible circuit netlists from L-Edit layouts. It can recognize active and passive devices, subcircuits, and most common device parameters. L-Edit/SPR™ performs standard cell place and route, padframe generation, and pad routing. Optional layout libraries are available for digital cells, analog cells, digital-to-analog and analog-to-digital cells. |
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